1. Field of the Invention
The present invention relates to telecommunication systems especially wireless systems, wireless transmitters and wireless receivers, especially those using the Bluetooth standard. The present invention also relates to semiconductor integrated circuits that implement a wireless receiver and/or a wireless transmitter especially those using the Bluetooth standard, as well as software for implementing the transmitter and/or receiver.
2. Technical Background
Version 2.0+EDR of the Bluetooth standards introduces an Enhanced Data Rate (EDR) operation. The EDR standard is an improvement over the Basic Rate standard. New modulation schemes: π/4-DQPSK and 8DPSK, are proposed as well as the conventional GFSK. The bandwidth of the channel is 1 MHz.
A Bluetooth transmitter is shown schematically in FIG. 1. The bits for transmission arrive at 1 Mbps, 2 Mbps or 3 Mbps and are coded in symbols “an” at 1 Msymbol per second. So the symbol time period “T” is 1 ps. The symbols are shaped with the SRRC filter and the modulated signal with a digital level can be produced using any whole multiple of 1 MHz. For example, 13 MHz can be used as this is an available clock in a Bluetooth system. Finally a Digital to analog converter (DAC ) is used to produce the analog modulated signal to be sent to the analog part of the transmitter.
A Bluetooth receiver has an analog front end and a digital part. At the Analog to Digital converter (ADC) in a Bluetooth receiver there are two simple possibilities for the sampling frequency: 13 MHz or 6.5 MHz. When operating at a sampling frequency of 6.5 MHz, theoretically the SRRC-receive filters (SRRC-Rx) could be matched to the SRRC-transmit filter (SRRC-Tx). However, the sampling frequency for the receiver has to be an integer multiple of the output frequency value of 1 MHz. One way is sampling at 13 MHz or even 26 MHz. This increases the complexity of the demodulator block, increases power consumption and cost. Another way of doing this is to provide an additional oscillator to generate a whole integer multiple frequency of 1 MHz lower than 13 MHz, e.g. 8 MHz, to clock the ADC and the other components of the digital part. Although sampling frequencies at lower frequencies such as 8 MHz can reduce the cost and complexity of the digital part of the receiver chain, it also reduces the accuracy of sample extraction as the number of samples per symbol is low.